Bus and Memory Transfer

In a multi register configuration system A bus structure is more efficient for transfer information from one register to other register.

A digital system composed of many registers, and paths must be provided to transfer information from one register to another. 

The number of wires connecting all of the registers will be excessive if separate lines are used between each register and all other registers in the system.

A bus structure, on the other hand, is more efficient for transferring information between registers in a multi-register configuration system.

In bus system control signals determine which register is selected by the bus during a particular register transfer.

The following block diagram shows a Bus system for four registers. It is constructed with the help of four 4 * 1 Multiplexers each having four data inputs (0 through 3) and two selection inputs (S1 and S2).

The four registers are named as Register A , Register B, Register C and Register D. The two selctor lines s1 and S2 are connected to the 4 multiplexers.based on selector line the out put of the 4*1 MUX is decided .Here we we used 4*1 multiplexer so we used 2 selector lines based on number of inputes to the mux the no of selectoe lines are lines are used here 4 = 2^2 so 2 selector lines are used . If 8*1 mux is used then 8 = 2^3 so three selector lines are required and so on.

Each bit of the register is connected to the one mux based on selector line input the output register is transfered.

The following function table shows the register that is selected by the bus for each of the four possible binary values of the Selection lines.

When both of the select lines are at low logic, i.e. S1S0 = 00, the 0 data inputs of all four multiplexers are selected and applied to the outputs that forms the bus. 

This, in turn, causes the bus lines to receive the content of register A since the outputs of this register are connected to the 0 data inputs of the multiplexers.

Similarly, when S1S0 = 01, register B is selected, and the bus lines will receive the content provided by register B.

Note: The number of multiplexers needed to construct the bus is equal to the number of bits in each register. The size of each multiplexer must be 'k * 1' since it multiplexes 'k' data lines. For instance, a common bus for eight registers of 16 bits each requires 16 multiplexers, one for each line in the bus. Each multiplexer must have eight data input lines and three selection lines to multiplex one significant bit in the eight registers.

A bus system can also be constructed using three-state gates instead of multiplexer.

The most commonly used three state gates in case of the bus system is a buffer gate.

The graphical symbol of a three-state buffer gate can be represented as:

• The outputs generated by the four buffers are connected to form a single bus line.
• Only one buffer can be in active state at a given point of time.
• The control inputs to the buffers determine which of the four normal inputs will communicate with the bus line
• .A 2 * 4 decoder ensures that no more than one control input is active at any given point of time.

Memory Transfer

standard notations used for specifying operations on memory transfer are:

• The reading of information from memory unit is called Read operation.
• writing the information in to the memory unit is called Write operation.
• A memory word is designated by the letter M.
• We must specify the address of memory word while writing the memory transfer operations.
• The address register is represented by AR and the data register by DR.
• Thus, a read operation can be represented as:                                                                           Read:  DR ← M [AR] 
• The Read statement causes a transfer of information into the data register (DR) from the memory word (M) selected by the address register (AR).
• The corresponding write operation can be stated as:                                                                    Write: M [AR] ← R1 
• The Write statement causes a transfer of information from register R1 into the memory word (M) selected by address register(AR).